4-1 tm CD4050BMS cmos hex buffer/converter the CD4050BMS is an non-inverting hex buffer and features logic level conversion using only one supply voltage (vcc). the input signal high level (vih) can exceed the vcc supply voltage when this device is used for logic level conversions. this device is intended for use as cmos to dtl/ttl converters and can drive directly two dtl/ttl loads. (vcc = 5v, vol 0.4v, and iol 3.3ma. the CD4050BMS is designated as replacement for cd4010b. because the CD4050BMS requires only one power supply, it is preferred over the cd4010b and should be used in place of the cd4010b in all inverter, current driver, or logic level conversion applications. in these appli- cations the CD4050BMS is pin compatible with the cd4010b, and can be substituted for this device in existing as well as in new designs. terminal no. 16 is not connected internally on the CD4050BMS, therefore, connection to this terminal is of no consequence to circuit operation. for appli- cations not requiring high sink current or voltage conversion, the cd4069ub hex inverter is recommended. the CD4050BMS is supplied in these 16 lead outline pack- ages: features ? high voltage type (20v rating) non-inverting type high sink current for driving 2 ttl loads high-to-low level logic conversion 100% tested for quiescent current at 20v maximum input current of 1 a at 18v over full pack- age temperature range; 100na at 18v and +25 o c 5v, 10v and 15v parametric ratings applications cmos to dtl/ttl hex converter cmos current ?sink? or ?source? driver cmos high-to-low logic level converter pinout CD4050BMS top view functional diagram schematic diagram figure 1. schematic diagram, 1 of 6 identical units braze seal dip h4t frit seal dip h1e ceramic flatpack h3x 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 vcc g = a a h = b b i = c vss c nc f nc k = e e j = d d l = f 32 ag = a 54 bh = b 76 ci = c 910 dj = d 11 12 ek = e 14 15 fl = f 1 8 vcc vss nc = 13 nc = 16 n p vcc r in out vss n p data sheet december 1992 fn3193 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
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4-3 absolute maximum ratings reliability information dc supply voltage range, (vdd) . . . . . . . . . . . . . . . . -0.5v to +20v (voltage referenced to vss terminals) input voltage range, all inputs . . . . . . . . . . . . . -0.5v to vdd +0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . 10ma operating temperature range . . . . . . . . . . . . . . . -55 o c to +125 o c package types d, f, k, h storage temperature range (tstg). . . . . . . . . . . -65 o c to +150 o c lead temperature (during soldering) . . . . . . . . . . . . . . . . . .+265 o c at distance 1/16 1/32 inch (1.59mm 0.79mm) from case for 10s maximum thermal resistance . . . . . . . . . . . . . . . . ja jc ceramic dip and frit package . . . . 80 o c/w 20 o c/w flatpack package. . . . . . . . . . . . . . . . 70 o c/w 20 o c/w maximum package power dissipation (pd) at +125 o c for ta = -55 o c to +100 o c (package type d, f, k) . . . . . .500mw for ta = +100 o c to +125 o c (package type d, f, k) . . . . derate linearity at 12mw/ o c to 200mw device dissipation per output transistor . . . . . . . . . . . . . . .100mw for ta = full package temperature range (all package types) junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175 o c table 1. dc electrical performance characteristics parameter symbol conditions (note 1) group a subgroups temperature limits units min max supply current idd vdd = 20v, vin = vdd or gnd 1 +25 o c-2 a 2+125 o c-200 a vdd = 18v, vin = vdd or gnd 3 -55 o c-2 a input leakage current iil vin = vdd or gnd vdd = 20 1 +25 o c-100-na 2+125 o c -1000 - na vdd = 18v 3 -55 o c-100-na input leakage current iih vin = vdd or gnd vdd = 20 1 +25 o c-100na 2+125 o c - 1000 na vdd = 18v 3 -55 o c-100na output voltage vol15 vdd = 15v, no load 1, 2, 3 +25 o c, +125 o c, -55 o c- 50 mv output voltage voh15 vdd = 15v, no load (note 3) 1, 2, 3 +25 o c, +125 o c, -55 o c14.95 - v output current (sink) iol4 vdd = 4.5v, vout = 0.4v 1 +25 o c2.6-ma output current (sink) iol5 vdd = 5v, vout = 0.4v 1 +25 o c3.2-ma output current (sink) iol10 vdd = 10v, vout = 0.5v 1 +25 o c8.0-ma output current (sink) iol15 vdd = 15v, vout = 1.5v 1 +25 o c24-ma output current (source) ioh5a vdd = 5v, vout = 4.6v 1 +25 o c--0.8ma output current (source) ioh5b vdd = 5v, vout = 2.5v 1 +25 o c--3.2ma output current (source) ioh10 vdd = 10v, vout = 9.5v 1 +25 o c--1.8ma output current (source) ioh15 vdd = 15v, vout = 13.5v 1 +25 o c--6.0ma n threshold voltage vnth vdd = 10v, iss = -10 a1+25 o c-2.8-0.7v p threshold voltage vpth vss = 0v, idd = 10 a1+25 o c0.72.8v functional f vdd = 2.8v, vin = vdd or gnd 7 +25 o cvoh > vdd/2 vol < vdd/2 v vdd = 20v, vin = vdd or gnd 7 +25 o c vdd = 18v, vin = vdd or gnd 8a +125 o c vdd = 3v, vin = vdd or gnd 8b -55 o c input voltage low (note 2) vil vdd = 5v, voh > 4.5v, vol < 0.5v 1, 2, 3 +25 o c, +125 o c, -55 o c- 1.5 v input voltage high (note 2) vih vdd = 5v, voh > 4.5v, vol < 0.5v 1, 2, 3 +25 o c, +125 o c, -55 o c3.5 - v input voltage low (note 2) vil vdd = 15v, voh > 13.5v, vol < 1.5v 1, 2, 3 +25 o c, +125 o c, -55 o c- 4 v input voltage high (note 2) vih vdd = 15v, voh > 13.5v, vol < 1.5v 1, 2, 3 +25 o c, +125 o c, -55 o c11 - v notes: 1. all voltages referenced to device gnd, 100% testing being im- plemented. 2. go/no go test with limits applied to inputs. 3. for accuracy, voltage is measured differentially to vdd. limit is 0.050v max. CD4050BMS
4-4 table 2. ac electrical performance characteristics parameter symbol conditions (note 1, 2) group a subgroups temperature limits units min max propagation delay tphl vdd = 5v, vin = vdd or gnd 9 +25 o c-110ns 10, 11 +125 o c, -55 o c- 149 ns propagation delay tplh vdd = 5v, vin = vdd or gnd 9 +25 o c-140ns 10, 11 +125 o c, -55 o c- 189 ns transition time tthl vdd = 5v, vin = vdd or gnd 9 +25 o c-60ns 10, 11 +125 o c, -55 o c- 81 ns transition time ttlh vdd = 5v, vin = vdd or gnd 9 +25 o c-160ns 10, 11 +125 o c, -55 o c- 216 ns notes: 1. cl = 50pf, rl = 200k, input tr, tf < 20ns. 2. -55 o c and +125 o c limits guaranteed, 100% testing being implemented. table 3. electrical performance characteristics parameter symbol conditions notes temperature limits units min max supply current idd vdd = 5v, vin = vdd or gnd 1, 2 -55 o c, +25 o c- 1 a +125 o c-30 a vdd = 10v, vin = vdd or gnd 1, 2 -55 o c, +25 o c- 2 a +125 o c-60 a vdd = 15v, vin = vdd or gnd 1, 2 -55 o c, +25 o c- 2 a +125 o c-120 a output voltage vol vdd = 5v, no load 1, 2 +25 o c, +125 o c, - 55 o c -50mv output voltage vol vdd = 10v, no load 1, 2 +25 o c, +125 o c, - 55 o c -50mv output voltage voh vdd = 5v, no load 1, 2 +25 o c, +125 o c, - 55 o c 4.95 - v output voltage voh vdd = 10v, no load 1, 2 +25 o c, +125 o c, - 55 o c 9.95 - v output current (sink) iol4 vdd = 4.5v, vout = 0.4v 1, 2 +125 o c1.8-ma -55 o c3.3-ma output current (sink) iol5 vdd = 5v, vout = 0.4v 1, 2 +125 o c2.4-ma -55 o c4.0-ma output current (sink) iol10 vdd = 10v, vout = 0.5v 1, 2 +125 o c5.6-ma -55 o c10-ma output current (sink) iol15 vdd = 15v, vout = 1.5v 1, 2 +125 o c18-ma -55 o c26-ma output current (source) ioh5a vdd = 5v, vout = 4.6v 1, 2 +125 o c--0.48ma -55 o c--0.81ma output current (source) ioh5b vdd = 5v, vout = 2.5v 1, 2 +125 o c--1.55ma -55 o c--2.6ma output current (source) ioh10 vdd = 10v, vout = 9.5v 1, 2 +125 o c--1.18ma -55 o c--2.0ma output current (source) ioh15 vdd =15v, vout = 13.5v 1, 2 +125 o c--3.1ma -55 o c--5.2ma CD4050BMS
4-5 input voltage low vil vdd = 10v, voh > 9v, vol < 1v 1, 2 +25 o c, +125 o c, - 55 o c -3v input voltage high vih vdd = 10v, voh > 9v, vol < 1v 1, 2 +25 o c, +125 o c, - 55 o c +7 - v propagation delay tphl vin = 10v, vdd = 5v 1, 2, 3 +25 o c-100ns vin = 10v, vdd = 10v 1, 2, 3 +25 o c-55ns propagation delay tplh vin = 10v, vdd = 5v 1, 2, 3 +25 o c-90ns vin = 10v, vdd = 10v 1, 2, 3 +25 o c-80ns propagation delay tphl vin = 15v, vdd = 5v 1, 2, 3 +25 o c-100ns vin = 15v, vdd = 15v 1, 2, 3 +25 o c-30ns propagation delay tplh vin = 15v, vdd = 5v 1, 2, 3 +25 o c-80ns vin = 15v, vdd = 15v 1, 2, 3 +25 o c-60ns transition time tthl vdd = 10v, vin = vdd or gnd 1, 2, 3 +25 o c-40ns vdd = 15v, vin = vdd or gnd 1, 2, 3 +25 o c-30ns transition time ttlh vdd = 10v, vin = vdd or gnd 1, 2, 3 +25 o c-80ns vdd = 15v, vin = vdd or gnd 1, 2, 3 +25 o c-60ns input capacitance cin any input 1, 2 +25 o c-7.5pf notes: 1. all voltages referenced to device gnd. 2. the parameters listed on table 3 are controlled via design or process and are not directly tested. these parameters are chara cterized on initial design release and upon design changes which would affect these characteristics. 3. cl = 50pf, rl = 200k, input tr, tf < 20ns. table 4. post irradiation electrical performance characteristics parameter symbol conditions notes temperature limits units min max supply current idd vdd = 20v, vin = vdd or gnd 1, 4 +25 o c-7.5 a n threshold voltage vnth vdd = 10v, iss = -10 a1, 4+25 o c-2.8-0.2v n threshold voltage delta ? vtn vdd = 10v, iss = -10 a1, 4+25 o c- 1v p threshold voltage vtp vss = 0v, idd = 10 a1, 4+25 o c0.22.8v p threshold voltage delta ? vtp vss = 0v, idd = 10 a1, 4+25 o c- 1v functional f vdd = 18v, vin = vdd or gnd 1 +25 o cvoh > vdd/2 vol < vdd/2 v vdd = 3v, vin = vdd or gnd propagation delay time tphl tplh vdd = 5v 1, 2, 3, 4 +25 o c - 1.35 x +25 o c limit ns notes: 1. all voltages referenced to device gnd. 2. cl = 50pf, rl = 200k, input tr, tf < 20ns. 3. see table 2 for +25 o c limit. 4. read and record table 5. burn-in and life test delta parameters +25 o c parameter symbol delta limit supply current - msi-1 idd 0.2 a output current (sink) iol5 20% x pre-test reading output current (source) ioh5a 20% x pre-test reading table 3. electrical performance characteristics (continued) parameter symbol conditions notes temperature limits units min max CD4050BMS
4-6 table 6. applicable subgroups conformance group mil-std-883 method group a subgroups read and record initial test (pre burn-in) 100% 5004 1, 7, 9 idd, iol5, ioh5a interim test 1 (post burn-in) 100% 5004 1, 7, 9 idd, iol5, ioh5a interim test 2 (post burn-in) 100% 5004 1, 7, 9 idd, iol5, ioh5a pda (note 1) 100% 5004 1, 7, 9, deltas interim test 3 (post burn-in) 100% 5004 1, 7, 9 idd, iol5, ioh5a pda (note 1) 100% 5004 1, 7, 9, deltas final test 100% 5004 2, 3, 8a, 8b, 10, 11 group a sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 group b subgroup b-5 sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11, deltas subgroups 1, 2, 3, 9, 10, 11 subgroup b-6 sample 5005 1, 7, 9 group d sample 5005 1, 2, 3, 8a, 8b, 9 subgroups 1, 2 3 note: 1. 5% parametric, 3% functional; cumulative for static 1 and 2. table 7. total dose irradiation conformance groups mil-std-883 method test read and record pre-irrad post-irrad pre-irrad post-irrad group e subgroup 2 5005 1, 7, 9 table 4 1, 9 table 4 table 8. burn-in and irradiation test connections function open ground vdd 9v -0.5v oscillator 50khz 25khz static burn-in 1 (note 1) 2, 4, 6, 10, 12, 13, 15 3, 5, 7-9, 11-14 1, 16 static burn-in 2 (note 1) 2, 4, 6, 10, 12, 13, 15 8 1, 3, 5, 7, 9, 11, 14, 16 dynamic burn-in (note 3) 13 8 1, 16 2, 4, 6, 10, 12, 15 3, 5, 7, 9, 11, 14 irradiation (note 2) 2, 4, 6, 10, 12, 13, 15, 16 8 1, 3, 5, 7, 9, 11, 14 notes: 1. each pin except pin 1, pin 16, and gnd will have a series resistor of 10k 5%, vdd = 18v 0.5v 2. each pin except pin 1, pin 16, and gnd will have a series resistor of 47k 5%; group e, subgroup 2, sample size is 4 dice/wafer, 0 failures, vdd = 10v 0.5v 3. each pin except pin 1, pin 16, and gnd will have a series resistor of 4.75k 5%, vdd = 10v 0.5v typical performance characteristics figure 2. minimum and maximum voltage transfer characteristics figure 3. typical output low (sink) current characteristics output voltage (vo) (v) 5 4 3 2 1 01234 input voltage (vi) (v) maximum minimum ambient temperature (t a ) = +25 o c supply voltage (vcc) = 5v 10v 15v ambient temperature (t a ) = +25 o c gate-to-source voltage (vgs) = 5v 0 30 20 10 40 50 60 drain-to-source voltage (vds) (v) output low (sink) current (iol) (ma) 12345678 70 CD4050BMS
4-7 figure 4. minimum output low (sink) current drain characteristics figure 5. typical output high (source) current characteristics figure 6. minimum output high (source) current characteristics figure 7. typical voltage transfer characteris- tics as a function of temperature figure 8. typical power dissipation vs frequency characteristics figure 9. typical power dissipation vs input rise and fall times per inverter typical performance characteristics (continued) 10v 15v ambient temperature (t a ) = +25 o c gate-to-source voltage (vgs) = 5v 0 30 20 10 40 50 60 drain-to-source voltage (vds) (v) output low (sink) current (iol) (ma) 12345678 70 -15v ambient temperature (t a ) = +25 o c gate-to-source voltage (vgs) = 5v -10v 0 drain-to-source voltage (vds) (v) -1 -2 -3 -4 -5 -6 -7 -8 output high (sink) current (ioh) (ma) -25 -30 -35 -20 -15 -10 -5 ambient temperature (t a ) = +25 o c gate-to-source voltage (vgs) = 5v -10v 0 drain-to-source voltage (vds) (v) -1 -2 -3 -4 -5 -6 -7 -8 output high (sink) current (ioh) (ma) -25 -30 -35 -20 -15 -10 -5 -15v 10 9 8 7 6 5 4 3 2 1 01 2345678910 output voltage (vo) (v) input voltage (vi) (v) supply voltage (vcc) = 10v ambient temp (t a ) = -55 o c vcc = 5v +125 o c +125 o c -55 o c 5v 10v 8 6 4 28 6 4 22 input frequency (f) (khz) 10 2 10 3 10 4 10 5 8 6 4 28 6 4 8 6 4 2 8 6 4 2 8 6 4 2 8 6 4 2 10 4 10 3 10 2 10 10 5 power dissipation per inverter ( w) supply voltage (vdd) = 15v ambient temperature (t a ) = +25 o c 10 10v cl = 15pf (11pf fixture + 4pf ext load capacitance (cl) = 50pf (11pf fixture + 39pf ext) input rise and fall time (tr, tf) (ns) 10 2 10 3 10 4 10 5 10 3 10 2 10 1 10 4 power dissipation per inverter (pd) ( w) 10 10 5 10 6 10 6 10 7 10 8 supply voltage (vcc) = 5v frequency (f) = 10khz 15v; 1khz 15v; 100khz 15v; 1mhz 10v; 100khz 15v; 10khz 10v; 10khz ambient temperature (t a ) = +25 o c CD4050BMS
4-8 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com chip dimensions and pad layout dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. grid graduations are in mils (10 -3 inch). metallization: thickness: 11k ? ? 14k ?, al. passivation: 10.4k? - 15.6k ? , silane bond pads: 0.004 inches x 0.004 inches min die thickness: 0.0198 inches - 0.0218 inches CD4050BMS
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